Dimensions change by temperature and limit the lithographical process. Lithography is one of the key steps in all semiconductor and electronic industries.  

The following is theoretical and based on pure calculations and some observations which I regard to be important to address when technology and solutions refines and takes new directions from what has been previously used.

To take full advantage of decreasing gate lengths, that drives the industry, it must be accomplished by higher interconnect density that requires increased precision between the following layers in the manufacturing process.  

Once physical dimensions shrink even very small amounts of energy that slightly changes temperature can become a significant issue in order to achieve precision.

The semiconductor industry roadmap, ITRS, does not according to last update as per May 2003 include this as a subject to be addressed.

 

 

 

Background.
Moore´s law has been ruling the semiconductor industry for several decades now.
All semiconductors are made by lithography as important and a limiting factor.
Lithography means to transfer pattern to a surface to be used for deposition and removal of sections on a substrate and by that creating areas of specific conducting properties like gates and interconnections.
Obstacles such as resolution of resists, surface accuracy, etching of structures and materials and impurities have so far been successfully concurred.

One of the remaining major issues now is how to generate patterned surfaces when the wavelength of light is too long to be able to focus in to the structures desired for next generation products.

 

 

 

NGL, Next Generation Lithography, comprise several solutions.

So far, temperature-induced physical deviation has been a minor problem as it only becomes significant in relation to overlay accuracy when several lithographic layers should interact.

Now reducing line widths and overall accuracy of pattern it will likely become an obstacle not easy to overcome.

Absolute thermal expansion (deviation) in substrate and relative between substrate and mask/stamp will by the reduction of physical dimensions of pattern become significant.
Optical, electron beam, nano imprint, hot embossing and possible also cold embossing all transfer energy that builds up heat in the substrate making it expand corresponding to its thermal expansion coefficient.
The thermal expansion coefficient is one of the basic parameters in physics.
The phenomena can be addressed to most types of lithography characterized by inducing energy in to the substrate.

Solving parallel exposure multiple layers and alignment issues such must be addressed not only at wafer level but also at the same time at single chip level.
Very small variations in temperature result in large deviations relative to pattern size.
Once the size of pattern comes down to single nm level even very small variation (change) in temperature will give significant deviation due to thermal expansion (or contraction). Overlay and CD, Critical Dimensions, must in this case be related to actual line widths and pattern size in general.

For steppers accumulated energy from each exposure step heats up the substrate so that the last exposure will be done on a slightly larger area relative to the first exposure.

The ability to maintain temperature and/or measurement control in lithography becomes extremely vital in future manufacturing.
It will be very important to be able to make corrections to the thermal deviation throughout the wafer and between individual exposure layers.

All lithography techniques induce energy into both substrate and mask rendering into rise of temperature. In steppers it is an accumulation by contribution from all the single steps makes each consecutive step a little different from previous exposures.

In optical lithography it can be anticipated that a certain area of the exposure field is exposed and that a certain part of the energy is transferred to heat (some energy is absorbed, some is reflected and some is transferred into chemical reaction.). It will be necessary to keep good control of physical deviation induced by photo radiation.

In several of lithography technologies energy is induced in the substrate and/or mask/stamper causing absolute and /or relative thermal expansion of both substrate and mask/stamper.
This becomes a very significant issue when decreasing pattern line widths and increasing exposed area.

The following tables and graphs show various situations that obviously speak for themselves.

 

 

 

DUV exposure

Temperature rise ºC of a 0,3mm thick silicon substrate by various DUV exposure densities and absorption (decreased reflection) at the substrate.
Calculation is made on a typical DUV exposure dose (50 mJ /cm sq)
Reflection of short wavelength light on silicon is supposed to be low, leaving the major exposure dose as heat on the substrate.

 

Calculation and relation of temperature rise of a substrate by light exposure on 100% area of Si 100mm (4”) substrate.

 

 

Table of temperature rise of a substrate by light exposure on limited area of Si 100mm (4”) substrate and by various levels of absorption.

Line marked by yellow is supposed to be typical.
Absorption in reality is expected to be typically more than 50%. (>60-70)

 

 

The graph and table show the physical deviation (expansion) related to increased temperature on 0,3mm thick Si chip 10x10mm, 5x5mm, 2,5x2,5mm.
Maximum deviation occurs in the diagonal.

Even small changes in temperature result in relative to nano pattern large deviation.
Example of 0,3mm thick Si chip 10x10mm with 50% exposed area and 50% absorption of light energy as shown in yellow marked table above result in about 8,8nm deviation.

In multiple layer applications and sub 100nm pattern, deviation is then 8,8% of pattern size due to thermal properties and despite any static alignment solution.
For pattern of less size relative deviation increases rapidly. 50nm pattern will give 17,6% deviation.

In steppers temperature gradually build up so that a single chip on a wafer expands and becomes slightly larger in area by the number of consecutive foregoing exposures done.
Temperature raises more, as substrates, wafers, tend to become thinner and mass being a function of thickness.

So, for the same example as above but with a 0,1mm thick chip temperature change is three times higher and also correspondent deviation.
Difference in temperature is directly related to total dose and exposure density, where an increased density increases temperature.
Exposure energy that heats up the substrates is only related to exposed area, absorption and dose.

Cooling that takes place by thermal contact is very small as the temperature difference is small between wafer and underlying substrate holder.
To obtain necessary overlay accuracy and CD it will be necessary to keep ambient conditions like temperature in manufacturing sites under extreme control.

Another design parameter is that as thermal deviation is related to total exposure dose including exposure density. Thermal deviation, expansion, is related exposure density with the same resist sensitivity.

The graph and table show the physical deviation (expansion) related to increased temperature on Si chip 10x10mm, 5x5mm, 2,5x2,5mm, but at higher temperatures.
Please notice ITRS roadmap 2002 update predictions of up to 26x26mm exposure field.

 

 

 

Nano imprint, hot embossing.
The graphs below show deviation over a 4” wafer.
The graph and table show the maximal physical deviation (expansion) of nickel stamper, Si substrate (wafer) and their relative deviation related to increased temperature over a 4” (100mm) Si wafer by nanoimprint or hot embossing.
(i.e. any contact printing comprising change of temperature of stamper/mold and substrate.)
The relative thermal deviation will also create “sliding” between stamper and substrate, taking away the ability to nanometer accuracy between layers.

In nano imprinting the actual imprint process may take place in a relatively small temperature interval. Even where the temperature interval is limited, deviation becomes significant.
Over 100mm the relative deviation is, as can be seen below, 1,07 um per degree C.
The same calculation model can be used in other combinations of materials and not only Ni and Si but also in other lithography methods like UV/DUV assisted contact printing.

UV assisted nano imprint where curing of resist is done over 100% of the substrate increases the temperature induced deviation independent from whether the imprint/exposure is done in one for the full substrate or in parts in several consecutive sequences.

All reproduction of pattern that involve change of temperature cause temporary misalignment between mask/stamp and substrate.

The misalignment occurs both when heating up and cooling and for NIL there is a phase shift in heating and cooling between mask/stamp and substrate causing a relative movement between the two in two occasions.

Glass temperature, at whatever level, for polymers normally takes place in a temperature span of several degrees C. Several degrees C of shift in temperature causes a relative to nano pattern a substantial displacement of pattern.
Control of temperature and relative “sliding” and misalignment between stamper and substrate has a time delay (hysterisis) due to thermal resistance and time.

 

There are several other technologies like using a “rubber stamp” to print ink to serve as a resist mask.
From presented diagrams it can clearly be seen that the problem with temperature is general as being related to thermally induced changes of any wafer and/or chip dimensions.
So even if rubber will remain stable? in its dimensions with regards to temperature there are just very small differences in temperature that makes major differences in CD.

Several applications in presented papers, demonstrate nano lithography show exposure density of 50%.
The graphs of temperature induced deviation above are “a little gentle” to the IRTS roadmap as the future preferred chip size is 572mm2 giving 2,6 times higher maximum deviation than a 100mm2 (10x10mm) chip will do.

The graph above shows deviation over 100mm. A lot of today’s production is 300mm with aim towards 450mm wafers. Thermally induced deviation corresponds directly to size so figures in the table above can be multiplied by 3 and 4,5.

If stamp is made out of silicon like the substrate to minimize different thermal deviation between stamp and substrate there is still a deviation due to thermal resistance and time delay in heating/cooling causing deviation.

If time for imprint process is increased the deviation will be reduced.
Over 100mm silicon only expands 260nm per degree C.

In applications where several consecutive “exposures” i.e. imprints shall be made it is not only in the imprint phase it is important to keep an extreme good temperature control.
All 1:1 exposure or imprint requires a mask or a stamp that has to be made under very strict temperature control in all manufacturing steps.

To achieve nano sized pattern it is most likely to use electron beam lithography to make the original pattern. From the first writing process through all following steps it is vital to keep track of the thermal deviation up to final imprint or exposure.

Such steps can be the manufacturing of a UV transparent or a nickel stamp, where as normally nickel stamps are made by electroforming in heated nickel deposition vats.

 

 

 

Summery and a conclusion
As production moves to smaller physical features there will be difficulties to overcome and possible also a new approach will be required in order to avoid and come across thermal deviation issues.

Figures from above are related to one single exposure/layer as for multiple layers deviation should be kept within absolute value. For two layers half the value for temperature deviation.

Optical lithography creates heating of substrates causing dimensions to change. Whatever cost will be spent on optical technology this will remain as a fact.
Sensitivity of resists can probably be increased in order to minimize heating, but as long as there is an exposure, there will be heating.

Increased thickness of the wafer can also serve to reduce thermal expansion, as mass increases reducing the rise of temperature. Double thickness gives half temperature rise.

The ability to maintain very accurate control of ambient and substrate temperature will be extremely important.
If reflection on the substrate can be increased by any means, thermal expansion will of course decrease.

There can be a technical window to do so, but it will probably require several other changes in downstream processing from todays.

Exposure density affects the temperature and thereby the expansion.
Masks for different exposure layers with different densities must also be compensated.

Nano imprint, NIL, is so far regarded to be one of the promising NGL due to several reasons like;
Ability to reproduce pattern down to single nanometer level, very low investment cost relative DUV, gentleness to substrate by absence of radiation, electrons, ion etc.

There are of course ways to reduce the major thermal influence by solutions like choice of imprint polymers with a narrower temperature window or by choice of stamper material with thermal expansion coefficient closer to that of substrate.

Thermal expansion creates relative movement between stamper and substrate and it will be important to control this by utilization of active feedback during process.
It will likely be necessary to use a well-defined, possibly fixed, reference point or points as the relative movement must be regarded as “floating”.

For use of NIL either non-CD applications and /or in applications where several layers can be produced by one multilevel tool is to be preferred, or in applications where the number of layers is reduced to one or may be two.

Thermal deviation must be considered once dimensions shrink whatever lithography concept will be used in the future.

In general, another way to overcome the CD thermal issues is to find solutions and design where overlay and CD will be avoided by some kind of a fuzzy logic approach where there are self-adjusting functions….

Something for the future…

 

Lennart Olsson

References: SIA ITRS Roadmap 2002 update http://public.itrs.net 

* Mr Moore refers to the Intel founder Gordon Moore